Can I turn the chip design if I do FPGA?

March 24, 2024
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1 Introduction

FPGA (Field-ProGramMable Gate Array) originated in the 1980s. It is a programmable logical circuit chip that can be used to achieve specific functions.Compared with the traditional ASIC (Application Specific Integrated Circuit) chip, the FPGA chip has higher flexibility and can modify logical design on -site programming, and it also has a high degree of reconstruction.So, the question of beginners is: Can FPGA be used to design?

2. The difference between FPGA and ASIC

When designing a chip, the logic circuit of the ASIC chip is solidified on the chip in the early stage of design, and is usually used to perform a specific function. Therefore, the ASIC chip can provide higher performance and power efficiency.However, the design process of the ASIC chip needs to customize the circuit, and it is necessary to deal with a large number of dealing with specific manufacturers and repeated work.The FPGA chip provides better flexibility and can be modified by programming, but its performance and power are usually slightly inferior to ASIC chips.

Cyclone II FPGA

3. The basic principle of FPGA to chip

Because the logic circuit of the FPGA chip is programable on the spot. When the design is completed, the FPGA chip cannot be directly converted into an ASIC chip due to the limitation of the component.In fact, the converting FPGA to ASIC requires a series of process steps such as logical synthesis, low -door comprehensive, layout, wiring, and layout.These steps may cause many problems, such as delay.

4. Logic comprehensive

Logic synthesis is the process of transforming the design of high -level hardware description language (HDL) into a door -level network watch (RTL).Logic synthesis will map the design parameters to the chip technology library of the target, including finding and replacing standard units, generating timing, and optimizing logical paths.The logical comprehensive output is the RTL code.

5. Low door -level comprehensive

The low -door comprehensive will turn the RTL code into a door -level circuit network table, mainly including various logical doors, registers and wiring switches, and so on.The low door -level comprehensive converts the RTL code into the timing animation based on the target chip, including door latency, queue time, register delay, and so on.The operation will output the circuit structure of the target chip.


6. layout

Layout is the process of flat logic circuit.Layout engineers will plan the door on the chip surface on the chip surface.For medium -density chips, the layout may take several hours or days, and the layout may take several weeks or months for high -density chips.

7. Wiring

Wiring is a process of connecting the transmission line on the chip.The wiring engine will generate a set of physical constraints for the given chip layout and connect the circuit circuit to the scope of these regulations.The output of the wiring is a complete circuit.

8. Farter

The layout is the final chip pattern generated after completing the layout and wiring. At the same time, the layout includes the technology library and SPI information used.


9. The tools required for FPGA to transfer chips

To convert FPGA design to ASIC design, a circuit design tool needs to be used.These include SynopSys circuit design and verification software, Cadence circuit design and verification software, MENTOR fluid mechanical circuit design and verification software, Apache circuit design and verification software.

10. Conclusion

It can be seen that FPGA converted into ASIC chips can be completed in the basic process, but many process steps are required, and the design after converting into ASIC usually needs to be more secure, simplified and have better compatibility than the original hardware configuration method.However, FPGA chips have better flexibility and reconstruction compared to traditional ASIC chips.

Then, for beginners, you should start with FPGA. First, you must be familiar with the basic design process of FPGA, practice design skills, and learn ASIC design work as needed in the future.