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Arria II FPGA Family
The Arria® II device family is designed specifically for ease of use. The cost-optimized, 40-nm device family architecture features a low-power, programmable logic engine and streamlined transceivers and I/Os. Common interfaces, such as the Physical Interface for PCI Express® (PCIe®), Ethernet, and DDR3 memory are easily implemented in your design with the Quartus® II software, the SOPC Builder design software, and a broad library of hard and soft intellectual property (IP) solutions from Altera. The Arria II device family makes designing for applications requiring transceivers operating at up to 6.375 Gbps fast and easy.
- 40-nm, low-power FPGA engine
- High-performance digital signal processing (DSP) blocks up to 550 MHz
- Up to 24 full-duplex clock data recovery (CDR)-based transceivers supporting rates between 600 Mbps and 6.375 Gbps
- Up to 726 user I/O pins arranged in up to 20 modular I/O banks that support a wide range of single-ended and differential I/O standards
- Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps
- Low cost, easy-to-use development kits featuring high-speed mezzanine connectors (HSMC)
What are the devices of Arria II FPGA?
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