MAX 3000A CPLD

MAX 3000A CPLD Family

MAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM–based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification.
The MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high–density small-scale integration (SSI), medium-scale integration (MSI), and large-scale integration (LSI) logic functions. The MAX 3000A architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices.
MAX 3000A devices are available in a wide range of packages, including PLCC, PQFP, and TQFP packages.
MAX 3000A devices use CMOS EEPROM cells to implement logic functions. The user–configurable MAX 3000A architecture accommodates a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations during design development and debugging cycles, and can be programmed and erased up to 100 times.

MAX 3000A Device Features

• High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture
• 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
• Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
• Enhanced ISP features
• High–density PLDs ranging from 600 to 10,000 usable gates
• 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz
• MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels
• Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages
• Hot–socketing support
• Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
• Industrial temperature range
• PCI compatible
• Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
• Programmable power–saving mode for a power reduction of over 50% in each macrocell