Looking for FPGA & IC chips inventory online?


intel altera

MAX 7000A CPLD Family

MAX 7000A (including MAX 7000AE) devices are high-density, high-performance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operations of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification.
The MAX 7000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density integration of SSI, MSI, and LSI logic functions. It easily integrates multiple devices including PALs, GALs, and 22V10s devices. MAX 7000A devices are available in a wide range of packages, including PLCC, BGA, FineLine BGA, Ultra FineLine BGA, PQFP, and TQFP packages.
MAX 7000A devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000A architecture accommodates a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles and can be programmed and erased up to 100 times.

MAX 7000A Device Features

  • High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architectures
  • 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with the advanced pin-locking capability
  • Built-in boundary-scan test (BST) circuitry is compliant with IEEE Std. 1149.1
  • Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71
  • Enhanced ISP features
  • Pin-compatible with the popular 5.0-V MAX 7000S devices
  • High-density PLDs ranging from 600 to 10,000 usable gates
  • Extended temperature range
  • 4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 MHz
  • Supports hot-socketing in MAX 7000AE devices
  • Programmable power-saving mode for 50% or greater power reduction in each macrocell
  • Software design support and automatic place-and-route provided by Altera’s development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations
  • Additional design entry and simulation support are provided by EDIF 2 0 0 and 3 0 0 netlist files, the library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
  • PCI-compatible
MAX 7000A Device Features

What are the devices of MAX 7000A CPLD?

Note: Only some components are listed, you can try the internal search of the site to find the components, or submit the RFQ below, we receive inquiries and will respond within 24 hours.

Submit Product RFQ