Stratix III

Stratix III FPGA Family

The Stratix® III family provides one of the most architecturally advanced, high-performance, low-power FPGAs in the marketplace.
Stratix III FPGAs lower power consumption through Altera’s innovative Programmable Power Technology, which provides the ability to turn on the performance where needed and turn down the power consumption for blocks not in use. Selectable Core Voltage and the latest in silicon process optimizations are also employed to deliver the industry’s lowest power, high-performance FPGAs.
Specifically designed for ease of use and rapid system integration, the Stratix III FPGA family offers two variants optimized to meet different application needs:
■ The Stratix III L family provides balanced logic, memory, and multiplier ratios for mainstream applications.
■ The Stratix III E family is memory- and multiplier-rich for data-centric applications.
Modular I/O banks with a common bank structure for vertical migration lend efficiency and flexibility to the high-speed I/O. Package and die enhancements with dynamic on-chip termination, output delay, and current strength control provide best-in-class signal integrity.
Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix III family is a programmable alternative to custom ASICs and programmable processors for high-performance logic, digital signal processing (DSP), and embedded designs.
Stratix III devices include optional configuration bit stream security through volatile or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where ultra-high reliability is required, Stratix III devices include automatic error detection circuitry to detect data corruption by soft errors in the configuration random-access memory (CRAM) and user memory cells.

Features

• 2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers
• Programmable Power Technology, which minimizes power while maximizing device performance
• Up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks per device
• Memory interface support with dedicated DQS logic on all I/O banks
• Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a wide range of industry I/O standards
• Support for multiple intellectual property megafunctions from Altera® MegaCore® functions and Altera Megafunction Partners Program (AMPPSM)