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Stratix FPGA Family

The Stratix® family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities of up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. Stratix devices offer up to 22 digital signal processing (DSP) blocks with up to 176 (9-bit × 9-bit) embedded multipliers, optimized for DSP applications that enable efficient implementation of high-performance filters and multipliers. Stratix devices support various I/O standards and also offer a complete clock management solution with its hierarchical clock structure with up to 420-MHz performance and up to 12 phase-locked loops (PLLs).


  • Up to 7,427,520 RAM bits(928,440 bytes) available without reducing logic resources
  • Up to 16 global clocks with 22 clocking resources per device region
  • Support for numerous single-ended and differential I/O standards
  • High-speed differential I/O support on up to 116 channels with up to 80 channels optimized for 840 megabits per second (Mbps)
  • Differential on-chip termination support for LVDS
  • High-speed DSP blocks provide dedicated implementation of multipliers (faster than 300 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters


Stratix Data Sheet

What are the devices of Stratix FPGA?

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