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LatticeECP2/M FPGA Family
The LatticeECP2/M family of FPGA devices is optimized to deliver high-performance features such as advanced DSP blocks, high-speed SERDES (LatticeECP2M family only), and high-speed source synchronous interfaces in an economical FPGA fabric. This combination was achieved through advances in device architecture and the use of 90nm technology.
The LatticeECP2/M family of FPGAs is designed to provide a low-cost alternative to high-end FPGAs while still delivering high-performance FPGA features. It includes features such as high-speed transceivers, hard IP blocks, memory interfaces, a built-in system clock, low power consumption, and the Secure Bitstream feature for encryption of the bitstream configuration file. Additionally, the LatticeECP2/M family offers SERDES, Dual Boot support, and encryption (S versions only). They have up to 95K LUTS, up to 5.3 Mbit block, and distributed RAM, and are able to interface to the Texas Instruments (TI) ADS644X and ADS642X family of ADC.
- Embedded SERDES supports data rates up to 3.125 Gbps (LatticeECP2M only)
- 3 to 42 blocks for high performance multiply and accumulate
- 55 Kbits to 5308 Kbits sysMEM™ Embedded Block RAM (EBR)
- Dedicated DDR and DDR2 memory support
- Two GPLLs and up to six SPLLs per device
- Available in TQFP, PQFP and fpBGA, packages
What are the devices of LatticeECP2/M FPGA?
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