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MachXO FPGA Family
The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs and low-capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip.
- Allows up to 100x static current reduction
- Up to 27.6 Kbits sysMEM™ Embedded Block RAM and up to 7.7Kbits distributed RAM
- IOs support LVCMOS, LVTTL, PCI, LVDS, Bus-LVDS, LVPECL, RSDS
- Up to two analog PLLs per device that enable clock multiplication, division, and phase shifting
- RAM based logic can be reconfigured in milliseconds using JTAG port
- Available in TQFP, csBGA, caBGA and ftBGA packages
What are the devices of MachXO FPGA?
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