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Lattice Semiconductor

MachXO2 FPGA Family

The MachXO2™ family of ultra-low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller, and timer/counter. These features allow these devices to be used in low-cost, high-volume consumer and system applications.
The MachXO2 devices are designed on a 65 nm nonvolatile low-power process. The device architecture has several features such as programmable low swing differential I/O and the ability to turn off I/O banks, onchip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power for all members of the family.


  • Six devices with 256 to 6864 LUT4s and 18 to 334 I/O
  • Advanced 65 nm low power process
  • As low as 22 μW standby power
  • Up to 240 kbits sysMEM™ Embedded Block RAM and up to 54 kbits Distributed RAM
  • Up to 256 kbits of User Flash Memory
  • Programmable sysIO™ buffer supports LVCMOS, LVTTL, PCI, LVDS, BLVDS, MLVDS, RSDS, LVPECL, SSTL, HSTL and more

What are the devices of MachXO2 FPGA?

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