MachXO3

MachXO3 FPGA Family

Lattice MachXO3™ device family is an Ultra-Low Density family that supports the most advanced programmable bridging and I/O expansion. It has the breakthrough I/O density and the lowest cost per I/O. The device I/O features have the integrated support for latest industry standard I/O.
The MachXO3L/LF family of low-power, instant-on, non-volatile PLDs has five devices with densities ranging from 640 to 9400 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. MachXO3LF devices also support User Flash Memory (UFM). These features allow these devices to be used in low cost, high volume applications such as consumer electronics, compute and storage, wireless communications, industrial control, and automotive systems.

Features

• Up to 9400 LUTs with up to 384 I/O pins
• MachXO3LF reconfigurable Flash includes 100,000 write/erase cycle for commercial/industrial devices and 10,000 for automotive devices
• Up to two edge clocks for high speed I/O interfaces (top and bottom sides only)
• Up to two analog PLLs per device with fractional-n frequency synthesis
• Available with 3.3/2.5 V core or low power 1.2 V core – including additional options on 9400 LUT devices
• On-chip hardened functions: SPI, I2C, timer/counter