Looking for FPGA & IC chips inventory online?


Lattice Semiconductor

MachXO3D FPGA Family

The MachXO3D™ device family is the next generation of Lattice Semiconductor Low-Density PLDs including enhanced security features and on-chip dual boot flash. The enhanced security features include Advanced Encryption Standard (AES) AES-128/256, Secure Hash Algorithm (SHA) SHA-256, Elliptic Curve Digital Signature Algorithm (ECDSA), Elliptic Curve Integrated Encryption Scheme (ECIES), Hash Message Authentication Code (HMAC) HMAC-SHA256, Public Key Cryptography, and Unique Secure ID. The MachXO3D family is a Root-of-Trust hardware solution that can easily scale to protect the whole system with its enhanced bitstream security and user mode functions. MachXO3D device provides breakthrough I/O density with high number of options for I/O programmability. The device I/O features the support for latest industry standard I/O, including programmable slew-rate enhancements and I3C support.


  • Logic Density ranging from 4.3k to 9.4k LUT4
  • High I/O to LUT ratio with up to 383 I/O pins
  • Programmable sysI/OTM buffer supports wide range of interfaces
  • Up to two edge clocks for high speed I/O interfaces (top and bottom sides only)
  • Two analog PLLs per device with fractional-n frequency synthesis
  • Enables comprehensive protection against a variety of threats by providing data security, equipment security, data authentication, design security and brand protection


  • Secure boot and Root of Trust
  • Consumer Electronics
  • Compute and Storage
  • Wireless Communications
  • Industrial Control Systems
  • Automotive System

MachXO3D Family Selection Guide

MachXO3D Family Selection Guide

What are the devices of MachXO3D FPGA?

Note: Only some components are listed, you can try the internal search of the site to find the components, or submit the RFQ below, we receive inquiries and will respond within 24 hours.

Submit Product RFQ